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Preliminary Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Features
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Description
The L7585F Full-Feature, Low-Power Subscriber Loop Interface Circuit (SLIC) and Switch integrates the battery feed, test access relay, and ringing relay that are necessary to interface a codec to the tip and ring of a subscriber loop into one low-power, low-cost package. It is built using a 90 V complementary bipolar (CBIC) process and a 320 V Bipolar-CMOSDMOS (BCDMOS) process. The device is available in a 44-pin PLCC package. The device can be connected directly to the Agere Systems Inc. T8531/T8532 16-Channel Programmable Codec Chip Set without the need for any ac interface components.
Low active power Quiet tip/ring polarity reversal Distortion-free on-hook transmission 35 V to 60 V power supply operation 14 operating states: -- Forward battery active -- Reverse battery active -- Ground start (3) -- Forward battery ring open -- Reverse battery ring open -- Reverse battery tip open -- High impedance -- Ringing (2) -- Low current (2) -- Disconnect Self-test in all operating states Independent, adjustable ac and dc parameters: -- Switchhook detector threshold -- Loop current limit -- dc feed resistance -- Termination impedance Integrated ringing access relay Integrated test-in relay Integrated relay driver Integrated ring trip detector Thermal protection 44-pin, surface-mount, plastic package (PLCC)
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L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Table of Contents
Contents Page Figures Page
Features ......................................................................1 Description...................................................................1 Architectural Diagram ..................................................3 Pin Information ............................................................4 Operating States..........................................................7 Forward Battery Active State ....................................7 Ground Start/Tip Open State ....................................7 Ground Start/Tip Ground State .................................8 Forward Battery Ring Open State .............................8 Ringing States (2) .....................................................8 Disconnect State .......................................................8 Forward Battery Low-Current Active State ...............8 High-Impedance States (2) .......................................8 Reverse Battery Active State ....................................8 Reverse Battery Tip Open State ...............................8 Ground Start/Tip Amplifier State ...............................9 Reverse Battery Ring Open State.............................9 Reverse Battery Low-Current Active State ...............9 Absolute Maximum Ratings (TA = 25 C).....................9 Electrical Characteristics ...........................................10 On-State Switch V-I Characteristics ..........................17 Applications ...............................................................18 Tip/Ring Protection .................................................18 NDET Under Fault Conditions ................................18 Power, Clocking, and Layout ..................................18 Ring Trip .................................................................19 False On-Hook Transients ......................................19 Application Diagram ..................................................20 Outline Diagram.........................................................21 44-Pin PLCC ...........................................................21 Ordering Information .................................................22
Figure 1. Architectural Diagram ................................. 3 Figure 2. 44-Pin Diagram (PLCC) ............................. 4 Figure 3. On-State Switch V-I Characteristics ......... 17 Figure 4. 16-Channel Line Card Solution ................ 20
Tables
Page
Table 1. Pin Descriptions ........................................... 5 Table 2. B0--B3 Input State Coding .......................... 7 Table 3. B4--B5 Input State Coding .......................... 7 Table 4. Operating Conditions and Powering .......... 10 Table 5. Ring Trip Detector ..................................... 10 Table 6. Battery Feed Characteristics ..................... 11 Table 7. Analog Signal Pins .................................... 12 Table 8. Transmission Characteristics .................... 13 Table 9. Data Interface and Logic (Logic Inputs [CLK, NCS, and B0--B5] and Outputs [NDET]) ........................................ 14 Table 10. Timing Requirements (CLK, B0--B5, and NCS) ................................................. 14 Table 11. Relay Driver (RDO) ................................. 14 Table 12. Ringing Return Access Switch (SW1) ..... 15 Table 13. Test-In Access Switches (SW3 and SW6) ....................................... 15 Table 14. Tip and Ring Break Switches (SW2 and SW4) ....................................... 16 Table 15. Tip and Ring Feedback Switches (SW2a and SW4a) ................................... 16 Table 16. Ringing Access Switch (SW5) ................. 17
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Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Architectural Diagram
NCS B5 B4 B3 B2 B1 B0 AGND VCCA ITR VITR TXI 100 k +5 A CLK NDET PARALLEL DATA LATCH AND LOGIC NPDAT NPDAR - REF SW1--SW6 CONTROL RD FB NRT NLC SWITCHHOOK DETECTOR + - ITR/198 +5 A 50 A FB SW1 45 TRNG TTI PT SW3 45 SW2 25 VBAT ITR TIP/RING CURRENT SENSE ITR RFR 20 AR - RTI SW6 SW4a DCOUT RSW SW5 RRNG GTO RTS RD +5 A RELAY DRIVER RING TRIP DETECTOR NRT FB1 dc FEEDBACK AND CURRENT LIMIT BUFFER VBAT NPDAR BUFFER NPDAT RFT 20 AT + ac INTERFACE + BUFFER - ac RCVN RCVP SW2a 4 k LCTH IN 2.4 V REFERENCE DCOUT VRTX + AX AAC VTX
RECTIFIER GAIN = 3 OUT
SW4 PR
dc
BUFFER
FB2
+5 D
+10 V 75 A VBAT IPROG DCR CF2 CF1
VBAT
RDO
DGND
VCCD
VSP
VBAT
BGND
12-3290.e(F)
Figure 1. Architectural Diagram
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L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Pin Information
DCOUT
AGND
RCVN
RCVP
VRTX 41
LCTH
IPROG
VCCA
DCR
6 CF1 FB2 FB1 BGND VBAT VBAT VSP NCS CLK NDET DGND 7 8 9 10 11 12 13 14 15 16 17 18 RDO
5
4
3
2
1
44
43
42
40 39 38 37 36 35 34 33 32 31 30 29 TXI VITR ITR BGND VBAT DGND VCCD B0 B1 B2 B3
19 RTS
20 RSW
21 RRNG
22 PR
23 RTI
24 TTI
25 PT
26 TRNG
27 B5
28 B4
VTX
CF2
12-2571(F).f
Figure 2. 44-Pin Diagram (PLCC)
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Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Pin Information (continued)
Table 1. Pin Descriptions Pin 1 2 3 4 5 Symbol VCCA LCTH IPROG DCOUT DCR Type -- I I O I Name/Function +5 V Analog dc Supply. +5 V supply for analog circuitry. Loop Closure Threshold Input. Connect a resistor to DCOUT to set the off-hook threshold. Current-Limit Program Input. A resistor to DCOUT sets the dc current limit. dc Output. This output is a voltage that is directly proportional to the differential tip/ring current. dc Resistance. Ground for dc feed resistance of 180 , or short to DCOUT for 600 . Intermediate values can be set with a resistor divider from DCOUT to ground, the tap of which is connected to DCR. Filter Capacitor 2. Connect a 0.1 F, 100 V capacitor from this pin to AGND and a 0.22 F, 100 V capacitor from this pin to pin CF1. Filter Capacitor 1. Connect a 0.22 F, 100 V capacitor from this pin to pin CF2. Forward Battery Slowdown 2. A capacitor from FB1 to AGND and from FB2 to AGND will ramp the polarity reversal transition when quiet polarity reversal is required. If not needed, the pin can be left open. Forward Battery Slowdown 1. A capacitor from FB1 to AGND and from FB2 to AGND will ramp the polarity reversal transition when quiet polarity reversal is required. If not needed, the pin can be left open. Battery Ground. Ground return for the battery (VBAT) supply. Battery Supply. Negative high-voltage power supply. Battery Supply. Negative high-voltage power supply. +10 V Supply. +10 V bias supply for switch circuitry. Not Channel Select. A low-to-high transition on this logic input stores the data on pins B0--B5 into the input latches on the SLIC. When NCS is either high or low, the SLIC is unaffected by data on pins B0--B5. Clock. Clock input. Not Detect. When low, this logic output indicates either a ring trip or an off-hook condition, depending on the input state of the SLIC. If either the BCDMOS portion or CBIC portion of this device enters thermal shutdown, NDET will be forced low. Digital Ground. Ground return for VCCD and relay driver flyback current. Relay Driver. This output drives an external relay. RDO is low (relay operated) when a low input on B5 is latched into the SLIC. Ring Trip Sense. Sense input for the ring trip detector. Ring Lead Ringing Access Switch. Ringing relay connects this pin to pin RRNG. Connect this pin to pin PR through a 500 current-limiting resistor. Ring Lead Ringing Supply. Connect this pin to the ringing supply. Protected Ring. The output of the ring driver and input to the transmit current sense circuit. Connect to the ring of the loop through overvoltage protection.
6 7 8
CF2 CF1 FB2
I/O I/O I
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FB1
I
10 11 12 13 14
BGND VBAT VBAT VSP NCS
-- -- -- -- I
15 16
CLK NDET
I O
17 18 19 20 21 22
DGND RDO RTS RSW RRNG PR
-- O I O I I/O
Note: On the printed-wiring board (PWB), make the leads to BGND and VBAT as wide as possible for thermal and electrical reasons. Also, maximize the amount of PWB copper on all leads connected to this device for the lowest operating temperature.
Agere Communications Inc.
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L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol RTI TTI PT TRNG B5 B4 B3 B2 B1 B0 VCCD DGND VBAT BGND ITR VITR TXI VTX VRTX RCVP RCVN AGND Type I I I/O O I I I I I I -- -- -- -- I O I O O I I -- Name/Function Ring Lead Test-In. Test-in relay connects this pin to PR. Connect RTI to the ring lead of the test-in bus. Tip Lead Test-In. Test-in relay connects this pin to PT. Connect TTI to the tip lead of the test-in bus. Protected Tip. The output of the tip driver and input to the transmit current sense circuit. Connect to the tip of the loop through overvoltage protection. Tip Lead Ringing Supply. Ringing relay connects this pin to PT. Connect TRNG to the ringing supply return. Bit 5. B0--B5 determine the state of the SLIC. See Operating States. Bit 4. B0--B5 determine the state of the SLIC. See Operating States. Bit 3. B0--B5 determine the state of the SLIC. See Operating States. Bit 2. B0--B5 determine the state of the SLIC. See Operating States. Bit 1. B0--B5 determine the state of the SLIC. See Operating States. Bit 0. B0--B5 determine the state of the SLIC. See Operating States. +5 V Digital dc Supply. +5 V supply for logic and switch circuitry. Digital Ground. Ground return for VCCD. Battery Supply. Negative high-voltage power supply. Battery Ground. Ground return for the battery (VBAT) supply. Tip/Ring Current. A current output which is proportional to the differential current flowing from tip to ring. Connect a resistor from this pin to VITR. Tip/Ring Voltage Output. The voltage at this output is directly proportional to the differential tip/ring current. A resistor from this pin to ITR sets the gain. Transmit ac Input. Connect a 0.1 F capacitor from this pin to VITR. Transmit ac Output Voltage. The ac voltage at this output is 7.2 times the ac voltage at pin TXI. The dc voltage is equal to the dc voltage on pin VRTX. Transmit ac Reference Voltage. The dc voltage at this output (2.4 V nominal) is the dc reference for the transmit signal output VTX. Receive ac Signal Input (Noninverting). This high-impedance input controls the ac differential voltage on tip and ring. Receive ac Signal Input (Inverting). This high-impedance input controls the ac differential voltage on tip and ring. Analog Ground. Ground return for VCCA.
Note: On the printed-wiring board (PWB), make the leads to BGND and VBAT as wide as possible for thermal and electrical reasons. Also, maximize the amount of PWB copper on all leads connected to this device for the lowest operating temperature.
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Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch Forward Battery Active State
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Operating States
The L7585 has 13 operating states. These states are selected using 4 bits, B0--B3, according to the truth table shown in Table 2. The operation of the L7585 is undefined for unassigned states. Additionally, bit B4 independently operates the test-in access contacts so that all states are available for self-test; and bit B5 independently operates a relay driver, regardless of the status of bits B0--B4. All 6 bits are loaded via the parallel data interface and chip select lead NCS. Table 2. B0--B3 Input State Coding B3 B2 B1 B0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 State Forward Battery Active Ground Start/Tip Open Ground Start/Tip Ground Forward Battery Ring Open Ringing (Battery Backed) Disconnect State Forward Battery Low Current Active State High Impedance Reverse Battery Active Reverse Battery Tip Open Ground Start/Tip Amplifier Reverse Battery Ring Open Ringing (Earth Backed) Unassigned Reverse Battery Low-Current Active State High Impedance
Normal talk and forward battery feed state. All circuits are powered up and active. Pin PT is positive with respect to pin PR (forward battery). SW2, SW2a, SW4, and SW4a closed; SW1, SW3, SW5, and SW6 open. NDET reflects the status of the switchhook detector.
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Ground Start/Tip Open State
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Ground start idle supervision state. Ring lead continuity test state (tone injected at the receive port) in forward battery. Same as forward battery active state, but with SW2 and SW2a open, and the tip drive amplifier powered down. Pin PT is high impedance (>100 k). The ring current limit is approximately equal to the value programmed for the high-current active state current limit. Current limit is achieved by reducing the ring lead voltage only (see Table 6). NDET indicates an off-hook when the ring current (flowing into PR) is twice the value programmed for the switchhook detector in the forward battery active state.
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Table 3. B4--B5 Input State Coding Bit B4 B5 1 0 1 0 State Test-in contacts off. Test-in contacts on. Relay driver off. Relay driver on.
Agere Communications Inc.
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L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Operating States (continued)
Ground Start/Tip Ground State
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Forward Battery Low-Current Active State
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Normal talk and forward battery feed state. All circuits are powered up and active. Pin PT is positive with respect to pin PR (forward battery). SW2, SW2a, SW4, and SW4a closed; SW1, SW3, SW5, and SW6 open. NDET reflects the status of the switchhook detector. Current limit is lowered to approximately 0.66 times the normal limit.
Ground start busy supervision state.
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Same as ground start/tip open state but with SW1 closed.
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Forward Battery Ring Open State
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Tip lead continuity test state (tone injected at the receive port) in forward battery. Same as forward battery active state, but with SW4 and SW4a open, and the ring drive amplifier powered down. Pin PR is high impedance (>100 k). Tip current limit is twice the low-current active state current limit. NDET indicates an off-hook when the tip current (flowing out of PT) is twice the value programmed for the switchhook detector in the forward battery active state.
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High-Impedance States (2)
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Disconnect state. Tip and ring drive amplifiers are powered down (all bias currents off). Pins PT and PR are high impedance (>100 k). SW1, SW2, SW2a, SW3, SW4, SW4a, SW5, and SW6 open. NDET is undefined.
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Ringing States (2)
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Reverse Battery Active State
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Normal ringing state. Tip and ring drive amplifiers are powered down.
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Normal talk and reverse battery feed state. Same as forward battery active state, but PR is positive with respect to PT.
SW1 and SW5 closed; SW2, SW2a, SW3, SW4, SW4a, and SW6 open. NDET reflects the status of the ring trip detector. Bit B3 indicates whether the ringing voltage applied to the ringing bus is either battery backed (B3 = 1) or earth backed (B3 = 0). Although B3 has no direct effect on the state of the SLIC, it can be used by the ring trip detector to enhance ring trip detection.
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Reverse Battery Tip Open State
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Ring lead continuity test state (tone injected at the receive port) in reverse battery. SW2 and SW2a open and the tip drive amplifier powered down. Pin PT is high impedance (>100 k). Pin PR is held between -1.7 V and -2.3 V for PR currents less than +-20 mA. PR current limit is the SW4 break switch current limit (250 mA < I < 85 mA). NDET indicates an off-hook when the ring current (flowing out of PR) is twice the value programmed for the switchhook detector in the reverse battery active state.
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Disconnect State
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All circuits are powered up and active. SW2, SW2a, SW4, and SW4a closed; SW1, SW3, SW5, and SW6 open. PT and PR are at the same potential to deny current to the loop.
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Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Operating States (continued)
Ground Start/Tip Amplifier State
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Absolute Maximum Ratings (TA = 25 C)
Stresses exceeding the values listed under absolute maximum ratings may cause permanent damage to the device. This is an absolute stress rating only. Functional operation of the device at these or any other conditions in excess of those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods of time may adversely affect device reliability. Parameter +5 V dc Supplies (VCCA and VCCD) +10 V dc Bias Supply (VSP) Office Battery Supply (VBAT) Logic Input Voltage Logic Input Clamp Diode Current, per Pin Logic Output Voltage Value -0.5 to +7.0 -0.5 to +15 -63 to +0.5 -0.5 to VDDD + 0.5 20 -0.5 to VDDD + 0.5 35 -40 to +125 -40 to +125 5 to 95 3 3 Unit V V V V mA V mA C C %RH V V
Current limiting is achieved by reducing ring lead voltage only. This state is the same as Ground Start/ Tip Open, but with SW2 and SW2A closed and the tip amplifier powered up. Ring lead current limit is approximately the difference of the high-current active state limit and the current flowing out of the tip lead. On-hook transmission not to exceed -3 dBm with up to 5 mA flowing out of the tip lead (maximum current flow into the tip lead is permissible). Larger signal and/or current may cause distortion. NDET indicates an off-hook when the current flowing out of the tip plus the current flowing into the ring is twice the value programmed for the switchhook detector.
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Reverse Battery Ring Open State
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Logic Output Current, per Pin (excluding relay driver) Operating Temperature Range Storage Temperature Range Relative Humidity Range Ground Potential Difference (BGND to AGND) Ground Potential Difference (DGND to AGND)
Note:
Tip lead continuity test state (tone injected at the receive port) in reverse battery. Same as reverse battery active state, but with SW4 and SW4a open, and the ring drive amplifier powered down. Pin PR is high impedance (>100 k). Tip current limit is twice the low-current active state current limit. NDET indicates an off-hook when the tip current (flowing into PT) is twice the value programmed for the switchhook detector in the reverse battery active state.
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Reverse Battery Low-Current Active State
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Normal talk and reverse battery feed state. Same as forward battery active state, but PR is positive with respect to PT. Current limit is lowered to approximately 0.66 times the normal limit.
Analog voltages are referenced to AGND, digital (logic) voltages are referenced to DGND, and battery voltages are referenced to BGND. The IC can be damaged unless all ground connections are applied before and are removed after all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. Some of the known examples of conditions that cause such potentials during powering are the following: 1) an inductor connected to tip and ring that can force an overvoltage on VBAT through external components if the VBAT connection chatters; and 2) inductance in the VBAT lead that could resonate with the VBAT filter capacitor to cause a destructive overvoltage.
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Agere Communications Inc.
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L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Electrical Characteristics
In general, minimum and maximum values are testing requirements. However, some parameters may not be tested in production because they are guaranteed by design and device characterization. Typical values reflect the design center or nominal value of the parameter; they are for information only and are not a requirement. Minimum and maximum values apply across the entire temperature range (-40 C to +85 C) and entire battery range (-35 V to -60 V). Unless otherwise specified, typical is defined as 25 C, VCCA = +5.0 V, VCCD = +5.0 V, VSP = +10 V, VBAT = -48 V. Positive currents flow into the device. Table 4. Operating Conditions and Powering Parameter Temperature Range Humidity Range Supply Voltages: VCCA VCCD VSP VBAT VCCA--VCCD DGND--AGND Supply Currents (all states, no loop current): ICCA + ICCD (+5 V) IVSP (+10 V) IBAT (-48 V) Total Power Dissipation (all states, no loop current) (VCC = +5 V; VSP = +10 V; VBAT = -48 V) Power Supply Rejection (tip/ring and transmit): VCCA (500 Hz--3 kHz; 50 mVrms ripple) VCCD (500 Hz--3 kHz; 50 mVrms ripple) VSP (500 Hz--3 kHz; 250 mVrms ripple) VBAT (500 Hz--3 kHz; 50 mVrms ripple) Thermal: Thermal Resistance (still air) Operating TJC Min -40 5 4.75 4.75 8.0 -35 -- -- -- -- -- -- Typ -- -- 5.0 5.0 10 -48 -- -- 4.9 45 -3.1 175 Max 85 95* 5.5 5.5 12.0 -60 0.5 0.25 7.0 200 -4.0 200 Unit C %RH V V V V V V mA A mA mW
30 45 45 45 -- --
40 -- -- -- -- --
-- -- -- -- 47 155
dB dB dB dB C/W C
* Not to exceed 26 grams of water per kilogram of dry air. This parameter is not tested in production; it is guaranteed by design and device characterization.
Table 5. Ring Trip Detector Parameter Voltage at input that will cause ring trip after appropriate zero crossings. Voltage at input that will cause immediate ring trip. Ringing Source1: Frequency (f) dc Voltage ac Voltage Ring Trip (NDET = 0)2, 3: Loop Resistance Trip Time NDET Valid Min 2.5 12 19 -39.5 60 2000 -- -- Typ 3 15 20 -- -- -- -- -- Max 3.5 18 28 -57 105 -- 200 80 Unit V V Hz V Vrms ms ms
1. The ringing source may be either of the following: a). The ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. In this case, bit B3 will always be a 1 when ringing is applied. b). The ringing source consists of only the ac voltage (earth-backed ringing); the ringing return is the dc voltage. In this case, bit B3 will always be a 0 when ringing is applied. 2. NDET must also indicate ring trip when the ac ringing voltage is absent (<5 Vrms) from the ringing source. 3. Pretrip ringing must not be tripped by a 10 k resistor in parallel with an 8 F capacitor applied across tip and ring.
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Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Table 6. Battery Feed Characteristics Parameter Tip or Ring Drive Current = dc + Longitudinal + Signal Currents ac Signal Current Longitudinal Current Capability per Wire1 dc Loop Current Limit2 (RLOOP = 100 ): Programmability Range Current Limit with VBAT = -51.5 V and RPROG = 64.9 k Low-current Mode2 (RLOOP = 100 , VBAT = -51.5 V, and RPROG = 64.9 k) Ground Start Ring Grounded (RLOOP = 100 ) Current Limit3: VBAT = -51.5 V, RPROG = 64.9 k Loop Closure Current Detector Threshold4 Programming Accuracy Open Loop Voltages (DCR = 0 V): Common-mode Voltage Differential Voltage Disconnect State PT/PR Voltage Ground Start Ring Lead Open or Shorted to Ground: PT and CF1 Voltage dc Feed Resistance: DCR Grounded DCR Connected to DCOUT5 dc Gains: PT/PR Current to DCOUT Voltage6: Forward Battery Reverse Battery DCR Voltage7 to PT/PR Differential Voltage Loop Resistance Range8 (3.17 dBm overload into 600 ): ILOOP = 20 mA at VBAT = -51.5 V Longitudinal to Metallic Balance--IEEE(R) Std. 455: 50 Hz to 1 kHz 1 kHz to 3 kHz Metallic to Longitudinal (harm) Balance: 200 Hz to 4 kHz
1. 2. 3. 4. 5. 6. 7. 8. 9.
Symbol -- -- -- ILIM
Min 65 10 8.5 5 44 25 38 --
Typ -- -- 15 -- 42 27.5 43 --
Max -- -- -- 45 56 30 47 7
Unit mA mArms mArms mA mA mA mA %
ILCD --
(VBAT + 1.8)/2 -- -- |VBAT + 7.0| |VBAT + 6.5| |VBAT + 6.0| |PT-PR| -- -1.7 -- 130 480 -- -118 118 3.13 -- 1890 -- 58 9 48 -- 35 -- -- 70 66 -- -- 1930 -- -- -- 3.33 -132 132 3.53 150 505 170 630 -2.0 -2.3 -- -- 100
V V mV V
V/A V/A --
dB dB dB
The longitudinal current is independent of dc loop current. Current limit, ILIM, is programmed by a resistor, RPROG, from pin IPROG to pin DCOUT. RPROG = 1.667 x (ILIM - 4); RPROG in k and ILIM in mA. The current limit versus loop voltage has a slope of 10 k. The low current mode current limit is approximately 0.66 times the high current limit. The ground start ring lead ground current limit is approximately equal to the high current limit and has a slope of about 5 k. In transmission applications, for compliance with TR-57, ground start ring lead I-V characteristics at high battery, it is expected that the high-current active current limit will be set to 28 mA. Loop closure detector current, ILCD, is programmed by a resistor, RLCTH, from pin LCTH to pin DCOUT. RLCTH = 2.5 x ILCD; RLCTH in k and ILCD in mA. ILCD is the tip to ring (forward battery) or ring to tip (reverse battery) current at which the loop closure detector indicates an off-hook. dc feed resistance may be adjusted between 180 and 600 using a resistor divider between DCOUT and DCR. The open loop differential voltage may also be increased by applying a negative voltage to pin DCR. See dc Gains, pin DCR. DCOUT gain depends on the resistor RGX1 from pin VITR to pin ITR. This gain assumes 8250 , the recommended value. Positive current is defined as the differential current flowing from PT to PR. Positive voltage on pin DCR has no effect on the PT/PR voltage. At tip and ring, assuming 82.5 protection resistors. At tip and ring with matched 82.5 protection resistors when feedback is connected for either 600 or 900 termination impedance.
Agere Communications Inc.
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L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Electrical Characteristics (continued)
Table 7. Analog Signal Pins Parameter DCOUT: Output Offset (no loop current) Output Drive Current Output Voltage Swing (+0.25 mA/-3 mA load): Maximum Minimum Output Short-circuit Current Output Load Resistance Output Load Capacitance1 VITR and VTX: Output Offset (no loop current)2 Output Drive Current Output Voltage Swing (1 mA load): Maximum Minimum (VITR) Minimum (VTX) Output Short-circuit Current Output Load Resistance Output Load Capacitance1 VRTX: Output Voltage Output Drive Current Output Short-circuit Current Output Load Capacitance1 RSW: Impedance to Ground DCR: Input Voltage Range3 Input Bias Current Input Impedance TXI: Input Impedance Input Voltage Compliance Input Clamp Voltage RCVP and RCVN: Input Voltage Range Input Bias Current Input Impedance PT and PR: Overvoltage (from external source; continuous) FB1 and FB2: ac Output Impedance Output Short-circuit Current CF1 and CF2: Output Impedance1 Min -- 0.25 VBAT -10 -- 5 -- -- 1 -10 3.5 -3.5 -- 4 -- 2.2 500 -- -- 3 -8 -- 500 75 0.4 0.4 -2.5 -- 10 -- -- 27 180 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 200 -3.0 VCCA 0.5 20 -- 50 100 -- VCCA -- VCCA - 1.0 20 -- 50 2.6 -- 15 50 -- 0 1 -- -- -- 0.8 VCCA 1.5 -- 265 10 34 375 Unit mV mA V V mA k pF mV mA V V V mA k pF V A mA pF M V A k k V V V A M V k A k
1. This parameter is not tested in production; it is guaranteed by design and device characterization. 2. VTX offset is measured with respect to pin VRTX. 3. Positive voltages from 0 V to VCCA are permitted at input DCR; however, voltages above 0 V have no effect on either the dc feed resistance or tip/ring voltage.
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Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Transmit direction is tip/ring to VTX. Receive direction is RCVP(N) to tip/ring. Table 8. Transmission Characteristics Parameter ac Termination
2
Min 200 25 29 -- -- -291 1.94
3
Typ -- -- -- -- -- -300 2
Max 1200 -- -- 0.3 1 -309 2.06
Unit dB dB % % V/A --
Impedance1
Return Loss : 200 Hz--500 Hz 500 Hz--3400 Hz Total Harmonic Distortion (200 Hz--4 kHz)3: Off-hook On-hook Transmit Gain (f = 1 kHz)4: PT/PR Current to (VTX--VRTX) Receive Gain (f = 1 kHz): (RCVP--RCVN) to (PT--PR) Gain vs. Frequency (transmit and receive) (600 termination; 1 kHz reference): 200 Hz--300 Hz 300 Hz--3.4 kHz 3.4 kHz--20 kHz 20 kHz--266 kHz
-0.3 -0.05 -3.0 -- -0.05 25 29 -- -- -- -- -- -- --
0 0 0 -- 0 -- -- -- -- -- -- -- -- --
0.05 0.05 0.05 2.0 0.05 -- -- -77 13 20 -77 13 20 -40
dB dB dB dB dB dB dB dBmp dBrnC dBrn dBmp0 dBrnC0 dBrn0 dBm, 600
Gain vs. Level (transmit and receive; 0 dBV reference)3: -50 dB to +3 dB Transhybrid Loss 200 Hz--500 Hz 500 Hz--3400 Hz Idle-channel Noise (tip/ring; 600 termination): Psophometric C-message 3 kHz Flat Idle-channel Noise ((VTX--VRTX); 600 termination): Psophometric C-message 3 kHz Flat EMC, per EN 300 386-2 and EN61000-4-6 (3 Vrms, 80% modulation, 105 kHz--80 MHz, 150 source impedance)3
2:
1. Set by external components in conjunction with the T7531A/T7536 codecs. Any complex impedance R1 + R2 || C between 200 and 1200 can be synthesized. 2. Return loss and transhybrid loss are functions of device gain accuracies and the external hybrid circuit. Guaranteed performance assumes 1% tolerance external resistors and capacitors. 3. This parameter is not tested in production; it is guaranteed by design and device characterization. 4. VTX gain depends on the resistor RGX1 from pin VITR to pin ITR. This gain assumes an ideal 8250 , the recommended value. Positive current is defined as the differential current flowing from PT to PR. The transmit signal at VTX is measured with respect to pin VRTX.
Agere Communications Inc.
13
L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Electrical Characteristics (continued)
Table 9. Data Interface and Logic (Logic Inputs [CLK, NCS, and B0--B5] and Outputs [NDET]) Parameter1 High-level Input Voltage Low-level Input Voltage Input Bias Current (high and low) High-level Output Voltage (IOUT = -100 A) Low-level Output Voltage (IOUT = 180 A) Output Short-circuit Current (VOUT = VCCD) Output Load Capacitance
2
Symbol VIH VIL IIN VOH VOL IOSS COL
Min 2 0 -- VCCD - 1.5 0 1 0
Max VCCD 0.8 10 VCCD 0.4 35 50
Unit V V A V V mA pF
1. Unless otherwise specified, all logic voltages are referenced to DGND. 2. This parameter is not tested in production; it is guaranteed by design and device characterization.
Table 10. Timing Requirements (CLK, B0--B5, and NCS)1, 2 Parameter CLK and NCS Rise and Fall Time (10% to 90%) Maximum Input Capacitance Minimum Setup Time from B0--B5 Valid to NCS VIH = 2 V VIH = 2.5 V Minimum Hold Time from NCS to B0--B5 Not Valid VIH = 2 V VIH = 2.5 V Minimum Pulse Width of NCS CLK Frequency Minimum Pulse Width of CLK Symbol tR, tF CIN tSDS tSDS tHDS tHDS tWCS fCLK tWCK Min 0 -- 250 150 150 10 195 0.9 195 Max 50 5 -- -- -- -- -- 2.2 -- Unit ns pF ns ns ns ns ns MHz ns
1. Unless otherwise specified, all times are measured from the 50% point of logic transitions. 2. These parameters are not tested in production; they are guaranteed by design and device characterization.
Table 11. Relay Driver (RDO) Parameter1 Off-state Output Current (VRDO = VCCD) On-state Output Voltage (IRDO = 40 mA) On-state Output Voltage (IRDO = 20 mA) Clamp Diode Reverse Current (VRDO = 0) Clamp Diode On Voltage (IRDO = 80 mA) Turn-on Time2 Turn-off Time2 Symbol IOFF VON VON IR VOC tON tOFF Min -- 0 0 -- 6 -- -- Max 10 0.60 0.40 10 20 10 10 Unit A V V A V s s
1. Unless otherwise specified, all logic voltages are referenced to DGND. 2. This parameter is not tested in production; it is guaranteed by design and device characterization.
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Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Table 12. Ringing Return Access Switch (SW1) Parameter Off-state: Maximum Differential Voltage dc Leakage Current (VSW = 320 V) Feedthrough Capacitance2 On-state (See On-State Switch V-I Characteristics section.): Resistance (RON) Maximum Differential Voltage (Vmax) Foldback Voltage Breakpoint 1 (V1) Foldback Voltage Breakpoint 2 (V2) Current Limit (ILIMIT1) Current Limit (ILIMIT2) dV/dT Sensitivity 2, 3 Min -- -- -- -- -- 120 200 120 2 -- Typ -- -- -- 45 -- -- -- 220 -- 200 Max 3201 10 15 90 3201 -- -- 360 -- 2000 Unit V A pF V V V mA mA V/s
1. At 25 C, maximum voltage rating has a temperature coefficient of +0.167 V/C. 2. This parameter is not tested in production; it is guaranteed by design and device characterization. 3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/s typical with no switch turn-on. In the case of dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/s and full voltage. A known condition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt induced switch turn-off. In this case, no damage shall occur for dV/dt up to 2000 V/s as guaranteed by design and characterization.
Table 13. Test-In Access Switches (SW3 and SW6) Parameter Off-state: Maximum Differential Voltage dc Leakage Current (VSW = 320 V) Feedthrough Capacitance2 On-state (See On-State Switch V-I Characteristics section.): Resistance (RON) Maximum Differential Voltage (Vmax) Current Limit (ILIMIT) Switches SW3 and SW63 dV/dT Sensitivity 2, 4
1. 2. 3. 4.
Min -- -- -- -- -- 85 --
Typ -- -- -- 45 -- -- 200
Max 3201 10 15 90 60 -- 2000
Unit V A pF V mA V/s
At 25 C, maximum voltage rating has a temperature coefficient of +0.167 V/C. This parameter is not tested in production; it is guaranteed by design and device characterization. Test in access switches current limit will be > tip and ring break switches current limit. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/s typical with no switch turn-on. In the case of dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/s and full voltage. A known condition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt induced switch turn-off. In this case, no damage shall occur for dV/dt up to 2000 V/s as guaranteed by design and characterization.
Agere Communications Inc.
15
L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Electrical Characteristics (continued)
Table 14. Tip and Ring Break Switches (SW2 and SW4) Parameter Off-state: Maximum Differential Voltage dc Leakage Current (VSW = 320 V) Feedthrough Capacitance2 On-state (See On-State Switch V-I Characteristics section.): Resistance (RON) Maximum Differential Voltage (Vmax) Foldback Voltage Breakpoint 1 (V1) Foldback Voltage Breakpoint 2 (V2) Current Limit (ILIMIT1) Current Limit (ILIMIT2) dV/dT Sensitivity 2, 3 Min -- -- -- -- -- 60 V1 + 0.5 85 2 -- Typ -- -- -- 25 -- -- -- 160 -- 200 Max 3201 20 50 50 3201 -- -- 250 -- 2000 Unit V A pF V V V mA mA V/s
1. At 25 C, maximum voltage rating has a temperature coefficient of +0.167 V/C. 2. This parameter is not tested in production; it is guaranteed by design and device characterization. 3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/s typical with no switch turn-on. In the case of dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/s and full voltage. A known condition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt induced switch turn-off. In this case, no damage shall occur for dV/dt up to 2000 V/s as guaranteed by design and characterization.
Table 15. Tip and Ring Feedback Switches (SW2a and SW4a) Parameter Off-state: Maximum Differential Voltage dc Leakage Current (VSW = 320 V) Feedthrough Capacitance 2 On-state (See On-State Switch V-I Characteristics section.): Resistance (RON) Maximum Differential Voltage (Vmax) Current Limit (ILIMIT) dV/dT Sensitivity2, 3 Min -- -- -- -- -- 0.5 -- Typ -- -- -- 4 -- -- 200 Max 3201 10 15 10 3201 20 2000 Unit V A pF k V mA V/s
1. At 25 C, maximum voltage rating has a temperature coefficient of +0.167 V/C. 2. This parameter is not tested in production; it is guaranteed by design and device characterization. 3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/s typical with no switch turn-on. In the case of dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/s and full voltage. A known condition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt induced switch turn-off. In this case, no damage shall occur for dV/dt up to 2000 V/s as guaranteed by design and characterization.
16
Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Electrical Characteristics (continued)
Table 16. Ringing Access Switch (SW5) Parameter Off-state: Maximum Differential Voltage dc Leakage Current (VSW = 500 V) dc Leakage Current (VSW = 250 V) Feedthrough Capacitance1 On-state (See On-State Switch V-I Characteristics section.): Crossover Offset Voltage (VOS; ISW = 1 mA) Resistance (RON) Surge Current (10 s x 1000 s pulse)1 Release Current1 dV/dT Sensitivity 1, 2 Common-mode Voltage (Maximum Either Switch Terminal with Respect to Ground) Min -- -- -- -- -- -- -- 0.1 -- -- Typ -- -- -- 1 -- -- -- -- 200 -- Max 475 20 1 -- 3 10 2.5 2 2000 320 Unit V A A pF V A mA V/s V
1. This parameter is not tested in production; it is guaranteed by design and device characterization. 2. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity. 3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dt sensitivity at 200 V/s typical with no switch turn-on. In the case of dV/dt induced turn-on at higher dV/dt and amplitude, the design objective is no damage to at least 2000 V/s and full voltage. A known condition that can cause damage is initial current flow prior to the application of the dV/dt and the sudden application of reverse bias with dV/dt induced switch turn-off. In this case, no damage shall occur for dV/dt up to 2000 V/s as guaranteed by design and characterization.
On-State Switch I-V Characteristics
ISW +ILIMIT
CURRENT LIMITING
ISW ILIM1 RON
ISW
2/3 RON -VMAX -V2 -V1 -1.5 RON +1.5 ILIM2 VSW +V1 +V2 +VMAX
2/3 RON -VMAX RON -1.5 V 2/3 RON RON -ILIMIT CURRENT LIMITING +1.5 V +VMAX VSW -VOS +VOS VSW
-ILIM2
-ILIM1
12-3291.a(F)
12-3292.a(F)
5-5990.c(F)
A. SW2a, SW3, SW4a, SW6
B. SW5
C. SW1, SW2, SW4
Figure 3. On-State Switch I-V Characteristics
Agere Communications Inc.
17
L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Applications
Tip/Ring Protection
The L7585 SLIC has integrated overvoltage tertiary protection diodes in the tip and ring paths. The device also has an integrated thermal shutdown circuit which places tip/ring drivers in a high-impedance state when the die temperature exceeds 160 C. The SLIC requires the following to survive lightning and power cross requirements:
s s s
s
In the ringing state, if the resistor between RSW and PR is open, there will likely be a large voltage at the ringing input (due to capacitive loading) and ring trip will be asserted after the second zero crossing of ringing. Because there is no guarantee of the load at PR in this condition, there can be no guarantee of the state on NDET in this condition. If the device enters into thermal shutdown due to a fault that causes an off-hook, the off-hook indication will be stable as the device cycles in and out of thermal shutdown. If the fault does not cause an offhook, NDET will cycle between on- and off-hook as the device cycles in and out of thermal shutdown.
s
Fusible elements or PTCs Current-limiting resistors A secondary protector
Power, Clocking, and Layout
The SLIC requires +5 V (VCCA and VCCD) and a negative battery voltage (VBAT) to operate. The integrated switches require a 10 V or 12 V supply (VSP) and a TTL clock (CLK) to operate. CLK requires a frequency between 1.0 MHz to 2.048 MHz with a 50% duty cycle. SW1, SW3, and SW6 will not operate without CLK applied. A four- or six-layer board is recommended. Analog and battery grounds should be laid out as a plane and a layer, and tied together at the device. Digital ground can also be tied to this plane or run separately. VSP is referenced to DGND. VCC can be run as individual traces and can reside on the same layer as signal paths. VCCA and VCCD can be tied together at the SLIC. Placement of the talk battery is not critical. The ring bus should be on a separate layer from the SLIC/codec interface signal leads and traces should run perpendicular if the traces must cross. TXI, VITR, and ITR are the sensitive nodes on the SLIC. Transmit runners should be run in pairs, and receive runners should be run in pairs between the SLIC and the codec. A channel-to-channel spacing should be maintained.
Thermal fuse/surge resistor modules that satisfy the various requirements can be purchased from MMCTM. Protection resistors should have a tolerance of 1% and a ratio tolerance of 0.5%. The suppressor breakover voltage of the secondary protector should be set as low as possible. Select a value just above the maximum peak ring signal and maximum battery voltage.
NDET Under Fault Condition
s
The state of NDET is not guaranteed with loss of battery. In the ringing state, RRNG floating or with only dc on the ringing source, NDET will produce an off-hook because there are not zero crossings of ringing to cause an on-hook. In the ringing state with only ac (>40 Vrms) on the ringing source, an on-hook will be produced after the second zero crossing of the ringing waveform, because there is no dc component to the ringing current.
s
s
18
Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch False On-Hook Transients
s
Applications (continued)
Ring Trip
Ring trip is set by the value of RS1. The ring trip threshold at the ring trip inputs is 2.5 V minimum, 3.5 V maximum. A resistor value of 500 , as shown in Figure 4, will set the ring trip current threshold to 6.0 mA typical. Ring trip is asserted upon entering the ringing mode until the second zero crossing of ringing. This is either a positive-going zero crossing between -40 V and -30 V at -50 V VBAT) or a negative-going zero crossing (between -10 V and -20 V at -50 V VBAT). The different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 V. Ring trip will not be asserted unless the ring trip threshold is exceeded for two zero crossings. This is either a positive-going zero crossing between -40 V and -30 V at -50 V VBAT) or a negative-going zero crossing (between -10 V and -20 V at -50 V VBAT). The different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 V. Note that since the ringing voltage is monitored at RSW, one zero crossing can occur at switch turn-on depending on initial conditions. Ring trip is asserted immediately if the ring trip input is 15 V 3 V.
If the L7585F is off-hook in the ground-start/tip open state, the ground-start/tip ground state, or the ground-start/tip amplifier state, due to an applied ring ground, and it is switched to the forward battery active state, it will not generate a false on-hook longer than 10 ms in duration. This applies for loop resistances of 0 to 2000 , providing that all of the following criteria are satisfied: -- A loop closure is applied before the L7585F switches to the forward battery active state. -- The loop closure resistance (telephone set) is less than 430 . -- The ring ground and loop closure are applied at the same end of the loop. -- If the ring ground is removed while the L7585F is in the forward battery active state, then the ring ground resistance must be greater than 225 when the dc current limit is 40 mA, or greater than 430 when the dc current is 28 mA.
Agere Communications Inc.
19
L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Application Diagram
+10 V -48 V CVB 0.1 F 100 V +5 V CVA 0.1 F 10 V
VSP VBAT BGND VCCA AGND DGND CVD 0.1 F +5 V RELAY K1 RINGING BUS (SEE BELOW) RS1 500 CRTF 0.1 F 50 V VCCD RDO CF2 TRNG RRNG DCR DCOUT IPROG RSW RPROG 64.9 k RLCTH 24.9 k 0.1 F CF2 0.1 F 100 V SLIC 0 L7585 FB1 FB2 CF1 CF1 0.22 F 100 V FB1* 0.047 F 100 V FB2* 0.047 F 100 V
+5 V
+5 V
+5 V 0.1 F 0.1 F
VDDD
VDDA
EARTH BACK RINGING
TRNG RRNG 0.1 F +5 V +5 V 0.1 F
VSSD
VSSA
OCTAL CONTROL 0.1 F LCTH RRTF INTERFACE INTERFACE VDD VDDA CHANNEL 1 M OSFS 0 VRN0 OSFS RTS RCVN UPCK RPR OSCK 82.5 OSCK PR UPCS DSP VRP0 MICRORCVP OSDR0 OSDR0 ASIC PROCESSOR RING UPDI 260 V OSDR1 OSDR1 VTX0 VTX UPDO SURGE OSDX0 OSDX0 CK16 PROTECTOR CODEC 0 RPT VRTX0 VRTX T8532 OSDX1 OSDX1 82.5 PT SCKSEL CHANNELS CCS0 CCS0 2.4 V TXI RSTB TIP RSTB 1--7 CDI CDO CB1 RTI TEST-IN SCK 0.1 F CDO CDI BUS VITR TTI 100 V SFS RGX1 TEST RSTB PCM 1 MHz SDR CLK 8.25 k VDDD ITR CLOCK BUS RSTB T8531A SDX TEST RSTB NDET NCS B5 B4 B3 B2 B1 B0 CDI STSXB CDO PCM OSFS INTERFACE OSCK PARALLEL DATA BUS TO MICROPROCESSOR CCS1 CCS1 CODEC 1 CHANNELS T8532 OSDR2 OSDR2 8--15 TRNG OSDR3 BATTERY BACK OSDR3 RINGING OSDX2 RRNG OSDX2 OSDX3 OSDX3 VDDA VSSA VDDD VSSD VSS VSSA
12-3351.R(F)
* Optional for quiet reverse battery. 4.096 MHz operation; for 2.048 MHz operation, tie SCKSEL to VSS.
Figure 4. 16-Channel Line Card Solution
20
Agere Communications Inc.
Data Sheet September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Outline Diagram
44-Pin PLCC
Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Communications Sales Representative.
17.65 MAX 16.66 MAX PIN #1 IDENTIFIER ZONE
6
1
40
7
39
16.66 MAX 17.65 MAX
17
29
18
28
4.57 MAX SEATING PLANE 1.27 TYP 0.53 MAX 0.51 MIN TYP 0.10
5-2506(F)r7
Agere Communications Inc.
21
L7585F Full-Feature, Low-Power SLIC and Switch
Data Sheet September 2001
Ordering Information
Device Part No. LUCL7585FP-D LUCL7585FP-DT Description Full-Feature, Low-Power SLIC and Switch Full-Feature, Low-Power SLIC and Switch Package 44-Pin PLCC (Dry Bag) 44-Pin PLCC (Tape and Reel, Dry Bag) Comcode 108417023 108417031
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. MMC is a trademark of Microelectronic Modules Corporation.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liab ility is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved
September 2001 DS01-312ALC (Replaces DS00-216ALC)

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